The present invention relates to a circuit arrangement having a load transistor and a current sensing transistor coupled to the load transistor.
In order to detect the current through a load transistor which serves for switching a load, it is known to connect in parallel with the load transistor a transistor as a current sensing transistor which is operated with the same operating point as the load transistor. FIG. 1 shows such a circuit arrangement, also referred to as a current sense arrangement, according to the prior art.
The circuit arrangement has a load transistor T1S, which is connected up in series with a load Z1S between a supply potential Vdd and a reference-ground potential GND. Arranged in parallel with the load transistor T1S is a current sensing transistor T2S, whose gate terminal is connected to the gate terminal of the load transistor T1S and whose drain terminal together with the drain terminal of the load transistor T1S is connected to a supply potential Vdd. A series circuit comprising a transistor T3S and a current sensing resistor Z2S is connected downstream of the source terminal of the current sensing transistor T2S. In this case, the transistor T3S is driven by means of a comparator K1S, which compares the source potentials of the load transistor T1S and of the current sensing transistor T2S with one another in order to set them to the same value. The current I2 through the current sensing transistor T2S is then proportional to the current I1 through the load transistor T1S, the ratio of these two currents depending on the ratio of the dimensions of the load transistor T1S and of the current sensing transistor T2S.
It is also known for a current supplied by a current sensing transistor in accordance with FIG. 1 to be fed to different application circuits than that illustrated in FIG. 1. In this case, in known circuit arrangements, a dedicated current sensing transistor is provided for each of the evaluation circuits.
The load transistor and the associated current sensing transistor are usually integrated in a chip, while evaluation circuits are integrated in a further chip. In this case, a line connection is required between each of the current sensing transistors in one chip and the associated processing circuit in the other chip, which means that each of these connections requires a contact pin on the first and second chips.
It is an aim of the present invention to provide a circuit arrangement for evaluating the load current of a load transistor which can be realized simply with known circuit means and in which, in particular, the abovementioned disadvantages do not occur.
The circuit arrangement according to the invention has a load transistor and a current sensing transistor coupled to the load transistor, wherein a switch arrangement having at least one first switch is connected downstream of the current sensing transistor in order to connect the current sensing transistor to a first or second evaluation circuit depending on a control signal.
The circuit arrangement according to the invention requires only one current sensing transistor, whose output current can be fed via the switch arrangement as required to one of the evaluation circuits.
In accordance with one embodiment of the invention, it is provided that the switch arrangement can be driven depending on a load path voltage (drain-source voltage) of the load transistor. It is thus possible to provide, as an evaluation circuit, circuit components which supplement the current sensing resistor to form a conventional current sense circuit according to FIG. 1, the current of the current sensing resistor being fed to this evaluation circuit only until a predetermined drain-source voltage of the load transistor is reached. Conventional current sense circuits supply a current signal which is proportional to the load current only when the load transistor is not yet in saturation, in other words when the drain-source voltage is below a saturation voltage. By means of the circuit arrangement according to the invention, the current of the current sensing resistor can be fed to another evaluation circuit when the drain-source voltage reaches the value of the saturation voltage and the current of the current sensing resistor can no longer be suitably evaluated anyway in the current sense arrangement.
In accordance with a further embodiment of the invention, it is provided that the load transistor and the current sensing transistor are integrated in a first chip, and that the switch arrangement and the first and second evaluation circuits are integrated in a second chip. In this embodiment of the invention, only one line connection is required between the first chip and the second chip in order to be able to feed the load current of the current sensing resistor to the evaluation circuits.